Module Hardcaml.Always

Always is a DSL that lets one describe a circuit in the same style as a Verliog always block.

if and switch control constructs are provided. (<--) is used for assignment.

Code is written as lists of assignments, if and control statements.

variables;

let r_sync = Reg_spec.create ~clock ~clear in
let var = wire (zero 8) in
let var = reg r_sync enable 8 in

assignment;

var <-- exp;

if statements;

if_ condition [ ... ] [ ... ]

switch statements;

switch condition [
  of_int ~width:3 0, [ ... ];
  of_int ~width:3 1, [ ... ];
  of_int ~width:3 2, [ ... ];
  of_int ~width:3 3, [ ... ];
]

signals;

let (s:signal) = q (v:guarded) in

compilation;

compile [ ... ]

example;

      let state = reg r_sync enable 2 in
      let a = wire 8 in
      compile [
        if_ (a.value ==:. 4) [
          a <-- of_int ~width:8 2
        ] [
          switch state.value [
          (of_int ~width:2 0) [
            a <--. 3;
            state <-- of_int ~width:2 1;
          ];
          (of_int ~width:2 1) [
            a <--. 2;
            state <-- of_int ~width:2 2;
          ];
          (of_int ~width:2 2) [
            a <--. 1;
            state <-- of_int ~width:2 3;
          ];
          (of_int ~width:2 3) [
            a <--. 0;
            state <-- of_int ~width:2 4;
          ]
        ]
      ];
      let state = state.value in
      let a = a.value in
      ....
module Variable : sig ... end

The type of variables in guarded assignments. Variables may be asychronous wires, or synchronous regs. The current value of the variable may be accessed through the value field below.

type t = private
| Assign of Variable.t * Signal.t
| If of Signal.t * t Base.list * t Base.list
| Switch of Signal.t * (Signal.t * t Base.list) Base.list
val sexp_of_t : t -> Sexplib0.Sexp.t
type always = t
type 'a case = 'a * t Base.list
type 'a cases = 'a case Base.list
val if_ : Signal.t -> t Base.list -> t Base.list -> t

if statement

val elif : Signal.t -> t Base.list -> t Base.list -> t Base.list

else if branch

val when_ : Signal.t -> t Base.list -> t

if sel then ... else

val unless : Signal.t -> t Base.list -> t

if sel then else ...

val switch : Signal.t -> Signal.t cases -> t

switch statement

val proc : t Base.list -> t

Allows sequences of expressions to be inserted into the code; a syntactic nicety.

val (<--) : Variable.t -> Signal.t -> t

assignment

val (<--.) : Variable.t -> Base.int -> t

assignment with an integer constant - width is inferred

module State_machine : sig ... end
val compile : t Base.list -> Base.unit

compile to structural code