Fifo (hardcaml.Hardcaml.Fifo)

type 'a t = {

q : 'a;

full : 'a;

empty : 'a;

nearly_full : 'a;

nearly_empty : 'a;

used : 'a;

}

val sexp_of_t : ( 'a -> Sexplib0.Sexp.t ) -> 'a0 t -> Sexplib0.Sexp.t

val iter : 'a t -> f:( 'a0 -> Base.unit ) -> Base.unit

val iter2 : 'a t -> 'b t -> f:( 'a0 -> 'b0 -> Base.unit ) -> Base.unit

val map : 'a t -> f:( 'a0 -> 'b ) -> 'b0 t

val map2 : 'a t -> 'b t -> f:( 'a0 -> 'b0 -> 'c ) -> 'c0 t

val to_list : 'a t -> 'a0 Base.list

val t : (Base.string * Base.int) t

val equal : 'a Base__Equal.equal -> 'a0 t Base__Equal.equal

val port_names : Base.string t

val port_widths : Base.int t

type tag

val tags : tag t

val to_alist : 'a t -> (tag * 'a0) Base.list

val of_alist : (tag * 'a) Base.list -> 'a0 t

val sum_of_port_widths : Base.int

module Unsafe_assoc_by_port_name : sig ... end

val zip : 'a t -> 'b t -> ('a0 * 'b0) t

val zip3 : 'a t -> 'b t -> 'c t -> ('a0 * 'b0 * 'c0) t

val zip4 : 'a t -> 'b t -> 'c t -> 'd t -> ('a0 * 'b0 * 'c0 * 'd0) t

val zip5 : 
  'a t ->
  'b t ->
  'c t ->
  'd t ->
  'e t ->
  ('a0 * 'b0 * 'c0 * 'd0 * 'e0) t

val map3 : 'a t -> 'b t -> 'c t -> f:( 'a0 -> 'b0 -> 'c0 -> 'd ) -> 'd0 t

val map4 : 
  'a t ->
  'b t ->
  'c t ->
  'd t ->
  f:( 'a0 -> 'b0 -> 'c0 -> 'd0 -> 'e ) ->
  'e0 t

val map5 : 
  'a t ->
  'b t ->
  'c t ->
  'd t ->
  'e t ->
  f:( 'a0 -> 'b0 -> 'c0 -> 'd0 -> 'e0 -> 'f ) ->
  'f0 t

val iter3 : 
  'a t ->
  'b t ->
  'c t ->
  f:( 'a0 -> 'b0 -> 'c0 -> Base.unit ) ->
  Base.unit

val iter4 : 
  'a t ->
  'b t ->
  'c t ->
  'd t ->
  f:( 'a0 -> 'b0 -> 'c0 -> 'd0 -> Base.unit ) ->
  Base.unit

val iter5 : 
  'a t ->
  'b t ->
  'c t ->
  'd t ->
  'e t ->
  f:( 'a0 -> 'b0 -> 'c0 -> 'd0 -> 'e0 -> Base.unit ) ->
  Base.unit

val fold : 'a t -> init:'acc -> f:( 'acc -> 'a0 -> 'acc ) -> 'acc

val fold2 : 
  'a t ->
  'b t ->
  init:'acc ->
  f:( 'acc -> 'a0 -> 'b0 -> 'acc ) ->
  'acc

val scan : 'a t -> init:'acc -> f:( 'acc -> 'a0 -> 'acc * 'b ) -> 'b0 t

val scan2 : 
  'a t ->
  'b t ->
  init:'acc ->
  f:( 'acc -> 'a0 -> 'b0 -> 'acc * 'c ) ->
  'c0 t

val offsets : ?rev:Base.bool -> Base.unit -> Base.int t

val of_interface_list : 'a t Base.list -> 'a0 Base.list t

val to_interface_list : 'a Base.list t -> 'a0 t Base.list

module All (M : Base.Monad.S) : sig ... end

val or_error_all : 'a Base.Or_error.t t -> 'a0 t Base.Or_error.t

module type Comb = sig ... end

module Make_comb (Comb : Comb.S) : sig ... end

module Of_bits : sig ... end

module Of_signal : sig ... end

module Of_always : sig ... end

module Names_and_widths : sig ... end

type 'a create_params =
  ?nearly_empty:Base.int ->
  ?nearly_full:Base.int ->
  ?overflow_check:Base.bool ->
  ?reset:Signal.t ->
  ?underflow_check:Base.bool ->
  ?ram_attributes:Rtl_attribute.t Base.list ->
  ?scope:Scope.t ->
  'a

type create_fifo =
  ( Base.unit ->
    capacity:Base.int ->
    clock:Signal.t ->
    clear:Signal.t ->
    wr:Signal.t ->
    d:Signal.t ->
    rd:Signal.t ->
    Signal.t t )
    create_params

module Kinded_fifo : sig ... end

Base RTL FIFO

val create : 
  ?showahead:Base.bool ->
  ?nearly_empty:Base.int ->
  ?nearly_full:Base.int ->
  ?overflow_check:Base.bool ->
  ?reset:Signal.t ->
  ?underflow_check:Base.bool ->
  ?ram_attributes:Rtl_attribute.t Base.list ->
  ?scope:Scope.t ->
  Base.unit ->
  capacity:Base.int ->
  clock:Signal.t ->
  clear:Signal.t ->
  wr:Signal.t ->
  d:Signal.t ->
  rd:Signal.t ->
  Signal.t Hardcaml__Fifo_intf.T.t

create ~clock ~clear ~wr ~d ~rd capacity builds a FIFO with capacity elements which is written with d when wr is high and read when rd is high.

The default reset configuration is to use a synchronous clr signal. An asynchronous rst may be optionally provided. One of clr or rst must be non-empty.

Optional overflow and underflow checking may be used. Data will not be written(/read) when the fifo is full(/empty) regardles or the wr/(rd) signals.

nearly_emtpy and nearly_full may be programmed to go high when the fifo is nearing an underflow or overflow state.

The showahead mode changes the read behaviour of the FIFO. When showahead is false read data is available 1 cycle after rd is high. With showahead true the data is available on the same cycle as rd is high. To support showahead behaviour the timing of the full/empty flag also changes (although they still correctly indicate when it is safe to read or write to the FIFO). showahead mode has some extra cost in terms of extra logic. The implementation ensures the output is registered and timing performance is good - nearly as fast as the underlying RAM allows..

Note; showahead is sometimes referred to as "first word fall through". It uses the write-before-read ram mode which is problematic in synthesis so we include special logic that performs collision detection.

The used output indicates the number of elements currently in the FIFO.

Functions to derive fifo architectures from other architecetures.

val showahead_fifo_of_classic_fifo : 
  Kinded_fifo.create_classic ->
  Kinded_fifo.create_showahead Base.Staged.t

Derived FIFO architectures.

val create_classic_with_extra_reg : 
  ?nearly_empty:Base.int ->
  ?nearly_full:Base.int ->
  ?overflow_check:Base.bool ->
  ?reset:Signal.t ->
  ?underflow_check:Base.bool ->
  ?ram_attributes:Rtl_attribute.t Base.list ->
  ?scope:Scope.t ->
  Base.unit ->
  capacity:Base.int ->
  clock:Signal.t ->
  clear:Signal.t ->
  wr:Signal.t ->
  d:Signal.t ->
  rd:Signal.t ->
  Signal.t Hardcaml__Fifo_intf.T.t

Adds an extra output register to the non-showahead fifo. This delays the output, but ensures there is no logic data on the fifo output. Adds an extra cycle of latency (2 cycles from write to empty low).

val create_showahead_from_classic : create_fifo

Constructs a showahead fifo from a non-showahead fifo. Only modifies the control flags. Has 2 cycles of latency.

val create_showahead_with_extra_reg : create_fifo

Constructs a fifo similarly to create_showahead_from_classic and ensures the output data is registered. Has 3 cycles of latency, but is slightly faster than create ~showahead:true - it seems to only be limited by the underlying RAM frequency.

module type Config = sig ... end

module With_interface (Config : Config) : sig ... end

Create FIFO using interfaces.