Graph (hardcaml.Hardcaml.Graph)

val write_dot_rank : Stdio.Out_channel.t -> Circuit.t -> Base.unit

val write_gdl : 
  ?names:Base.bool ->
  ?widths:Base.bool ->
  ?consts:Base.bool ->
  ?clocks:Base.bool ->
  Stdio.Out_channel.t ->
  Circuit.t ->
  Base.unit

write a GDL (graph description language) file of the given circuit

val aisee3 : 
  ?args:Base.string ->
  ?names:Base.bool ->
  ?widths:Base.bool ->
  ?consts:Base.bool ->
  ?clocks:Base.bool ->
  Circuit.t ->
  Base.unit

launch aisee3 to visualize the given circuit