Make (hardcaml.Hardcaml.Interface.Make)

Parameters

module X : Pre

val sexp_of_t : ( 'a -> Sexplib0.Sexp.t ) -> 'a X.t -> Sexplib0.Sexp.t

val iter : 'a X.t -> f:( 'a -> Base.unit ) -> Base.unit

val iter2 : 'a X.t -> 'b X.t -> f:( 'a -> 'b -> Base.unit ) -> Base.unit

val map : 'a X.t -> f:( 'a -> 'b ) -> 'b X.t

val map2 : 'a X.t -> 'b X.t -> f:( 'a -> 'b -> 'c ) -> 'c X.t

val to_list : 'a X.t -> 'a Base.list

val t : (Base.string * Base.int) X.t

include Base.Equal.S1 with type 'a t := 'a X.t

val equal : 'a Base__Equal.equal -> 'a X.t Base__Equal.equal

val port_names : Base.string X.t

RTL names specified in the interface definition - commonly also the OCaml field name.

val port_widths : Base.int X.t

Bit widths specified in the interface definition.

type tag

val tags : tag X.t

val to_alist : 'a X.t -> (tag * 'a) Base.list

Create association list indexed by tag.

val of_alist : (tag * 'a) Base.list -> 'a X.t

Create interface from association list indexed by tag.

val sum_of_port_widths : Base.int

Sum of all port widths specified in the interface definition.

module Unsafe_assoc_by_port_name : sig ... end

val zip : 'a X.t -> 'b X.t -> ('a * 'b) X.t

val zip3 : 'a X.t -> 'b X.t -> 'c X.t -> ('a * 'b * 'c) X.t

val zip4 : 'a X.t -> 'b X.t -> 'c X.t -> 'd X.t -> ('a * 'b * 'c * 'd) X.t

val zip5 : 
  'a X.t ->
  'b X.t ->
  'c X.t ->
  'd X.t ->
  'e X.t ->
  ('a * 'b * 'c * 'd * 'e) X.t

val map3 : 'a X.t -> 'b X.t -> 'c X.t -> f:( 'a -> 'b -> 'c -> 'd ) -> 'd X.t

val map4 : 
  'a X.t ->
  'b X.t ->
  'c X.t ->
  'd X.t ->
  f:( 'a -> 'b -> 'c -> 'd -> 'e ) ->
  'e X.t

val map5 : 
  'a X.t ->
  'b X.t ->
  'c X.t ->
  'd X.t ->
  'e X.t ->
  f:( 'a -> 'b -> 'c -> 'd -> 'e -> 'f ) ->
  'f X.t

val iter3 : 
  'a X.t ->
  'b X.t ->
  'c X.t ->
  f:( 'a -> 'b -> 'c -> Base.unit ) ->
  Base.unit

val iter4 : 
  'a X.t ->
  'b X.t ->
  'c X.t ->
  'd X.t ->
  f:( 'a -> 'b -> 'c -> 'd -> Base.unit ) ->
  Base.unit

val iter5 : 
  'a X.t ->
  'b X.t ->
  'c X.t ->
  'd X.t ->
  'e X.t ->
  f:( 'a -> 'b -> 'c -> 'd -> 'e -> Base.unit ) ->
  Base.unit

val fold : 'a X.t -> init:'acc -> f:( 'acc -> 'a -> 'acc ) -> 'acc

val fold2 : 
  'a X.t ->
  'b X.t ->
  init:'acc ->
  f:( 'acc -> 'a -> 'b -> 'acc ) ->
  'acc

val scan : 'a X.t -> init:'acc -> f:( 'acc -> 'a -> 'acc * 'b ) -> 'b X.t

val scan2 : 
  'a X.t ->
  'b X.t ->
  init:'acc ->
  f:( 'acc -> 'a -> 'b -> 'acc * 'c ) ->
  'c X.t

val offsets : ?rev:Base.bool -> Base.unit -> Base.int X.t

Offset of each field within the interface. The first field is placed at the least significant bit, unless the rev argument is true.

val of_interface_list : 'a X.t Base.list -> 'a Base.list X.t

Take a list of interfaces and produce a single interface where each field is a list.

val to_interface_list : 'a Base.list X.t -> 'a X.t Base.list

Create a list of interfaces from a single interface where each field is a list. Raises if all lists don't have the same length.

module All (M : Base.Monad.S) : sig ... end

Similar to Monad.all for lists -- combine and lift the monads to outside the interface.

val or_error_all : 'a Base.Or_error.t X.t -> 'a X.t Base.Or_error.t

Equivalent to All(Or_error).all. This is made a special case for convenience.

module type Comb = sig ... end

module Make_comb (Comb : Comb.S) : Comb with type comb = Comb.t

module Of_bits : Comb with type comb = Bits.t

module Of_signal : sig ... end

module Of_always : sig ... end

Helper functions to ease usage of the Always API when working with interfaces.

module Names_and_widths : sig ... end