Module Rtl.Output_mode

RTL generation options.

type t =
| In_directory of Base.string(*

Write each circuit into a file in the given directory. The file name consists of the circuit name and the approriate file extension (.v for Verilog and .vhd for VHDL).

*)
| To_buffer of Base.Buffer.t(*

Write all circuits into one buffer.

*)
| To_channel of Stdio.Out_channel.t(*

Write all circuits to one out channel.

*)
| To_file of Base.string(*

Write all circuits into one file.

*)
val sexp_of_t : t -> Sexplib0.Sexp.t