Module Rtl_attribute.Vivado

A collection of common Xilinx Vivado attributes.

val async_reg : bool -> t

Inform Vivado that a registers data input is asychronous to it's clock.

val dont_touch : bool -> t

Instruct the synthesizer and place & route tools to keep the node. Cannot be applied to a port.

val keep_hierarchy : bool -> t

Setting keep_hierarchy to yes will prevent Vivado from optimizating across module boundaries. Can only be applied to modules or instances.

val fsm_encoding : [ `auto | `gray | `johnson | `none | `one_hot | `sequential ] -> t

Select encoding of finite state machine. Apply to state register.

val mark_debug : bool -> t

Export net for debugging with chipscope.

val keep : bool -> t

Similar to dont_touch

module Ram_style : sig ... end
module Srl_style : sig ... end

SRL_STYLE instructs the synthesis tool on how to infer SRLs that are found in the design. Accepted values are