Module Scope.Naming_scheme

Control of name generation in a hierarchy of modules. The position of a module within a hierarchy is determined by a path which leads back to the (single) top most parent module. Signal names may be pre-pended with some representation of that path.

Generally hierarchical names are taken from the circuit name, though it is possible to specify a different instantiation name. These names are mangled so they are unique within each scope.

type t =
| Full_path
| Local_path
| No_path
val sexp_of_t : t -> Sexplib0.Sexp.t