Module Signal.Reg_spec_

Reg_spec_ is a register specification. It is named Reg_spec_ rather than Reg_spec so that people consistently use the name Hardcaml.Reg_spec rather than Hardcaml.Signal.Reg_spec_.

type t = register
val sexp_of_t : t -> Sexplib0.Sexp.t
val create : ?clear:signal -> ?reset:signal -> Base.unit -> clock:signal -> t
val override : ?clock:signal -> ?clock_edge:Edge.t -> ?reset:signal -> ?reset_edge:Edge.t -> ?reset_to:signal -> ?clear:signal -> ?clear_level:Level.t -> ?clear_to:signal -> ?global_enable:signal -> t -> t
val clock : t -> signal
val clear : t -> signal
val reset : t -> signal