Module Hardcaml_circuits.Pipelined_incrementer

Simple pipelined incrementer.

val create : part_width:Base.int -> clock:Hardcaml.Signal.t -> clear:Hardcaml.Signal.t -> set:Hardcaml.Signal.t Hardcaml.With_valid.t -> increment:Hardcaml.Signal.t -> Hardcaml.Signal.t

Split the addition into width / part_width sub-adders. The increment value must be no wider than part_width.

The value can be set at any time.