Module Hardcaml_circuits.Pipelined_tree_mux

val pipelined_tree_mux : cycles:int -> reg:( Hardcaml.Signal.t -> Hardcaml.Signal.t ) -> selector:Hardcaml.Signal.t -> Hardcaml.Signal.t list -> Hardcaml.Signal.t
val pipelined_tree_priority_select : ?trace_reductions:bool -> cycles:int -> reg:( Hardcaml.Signal.t -> Hardcaml.Signal.t ) -> Hardcaml.Signal.t Hardcaml.With_valid.t list -> Hardcaml.Signal.t Hardcaml.With_valid.t