Hardcaml_circuits.Pipelined_tree_reducePipelined tree reduce operation, with propogation delay equivalent to ceil(log(|args|))
val create :
f:( Hardcaml.Signal.t -> Hardcaml.Signal.t -> Hardcaml.Signal.t ) ->
enable:Hardcaml.Signal.t ->
arity:Base.int ->
Hardcaml.Signal.register ->
Hardcaml.Signal.t Base.list ->
Hardcaml.Signal.t Hardcaml.With_valid.t