Expert.Port
Simulation port description.
module Type : sig ... end
type t = {
type_ : Type.t;
port_name : Hardcaml_waveterm__Port_name.t;
width : Base.int;
}
include Ppx_compare_lib.Comparable.S with type t := t
val compare : t Base__Ppx_compare_lib.compare
val sexp_of_t : t -> Sexplib0.Sexp.t
include Ppx_compare_lib.Equal.S with type t := t
val equal : t Base__Ppx_compare_lib.equal