Module Hardcaml_xilinx.Dual_port_ram

Single clock Dual Port Memory

val create : ?read_latency:Base.int -> ?arch:Ram_arch.t -> ?byte_write_width:Byte_write_width.t -> ?memory_optimization:Base.bool -> ?cascade_height:Cascade_height.t -> ?simulation_name:Base.string -> build_mode:Hardcaml.Build_mode.t -> Base.unit -> clock:Hardcaml.Signal.t -> clear:Hardcaml.Signal.t -> size:Base.int -> port_a:Hardcaml.Signal.t Ram_port.t -> port_b:Hardcaml.Signal.t Ram_port.t -> Hardcaml.Signal.t * Hardcaml.Signal.t

Create a Xilinx compatible memory. Uses True_dual_port_ram with appropriate parameters for implementation.