Memory_builder.Create
module M : Hardcaml.Interface.S
val create_simple_1d :
?name:Base.string ->
?simulation_name:Base.string ->
instance:Base.string ->
build_mode:Hardcaml.Build_mode.t ->
depth:Base.int ->
ram_read_latency:Base.int ->
how_to_instantiate_ram:Config.how_to_instantiate_ram ->
scope:Hardcaml.Scope.t ->
clock:Hardcaml.Signal.t ->
clear:Hardcaml.Signal.t ->
Base.unit ->
Hardcaml.Signal.t M.t t
val create :
?name:Base.string ->
instance:Base.string ->
build_mode:Hardcaml.Build_mode.t ->
config:Config.t ->
scope:Hardcaml.Scope.t ->
clock:Hardcaml.Signal.t ->
clear:Hardcaml.Signal.t ->
Base.unit ->
Hardcaml.Signal.t M.t t