Read_port_1d (hardcaml_xilinx.Hardcaml_xilinx.Memory_builder.Read_port

type 'a t = {

address : 'a;

enable : 'a;

}

val sexp_of_t : ( 'a -> Sexplib0.Sexp.t ) -> 'a t -> Sexplib0.Sexp.t

module type S = Hardcaml.Interface.S with type 'a t = 'a t

module Specialize (_ : Widths_1d) : S

Specialize a Read_port_1d.t given widths.

module Specialize_with_config (_ : Config.S) : S

Specialize a Read_port_1d.t given a memory configuration.