Write_port_1d (hardcaml_xilinx.Hardcaml_xilinx.Memory_builder.Write_port

type ('a, 'write_data) t = {

address : 'a;

enable : 'a;

data : 'write_data;

}

val sexp_of_t : 
  ( 'a -> Sexplib0.Sexp.t ) ->
  ( 'write_data -> Sexplib0.Sexp.t ) ->
  ( 'a, 'write_data ) t ->
  Sexplib0.Sexp.t

module type S = sig ... end

module Specialize
  (M : Hardcaml.Interface.S)
  (_ : Widths_1d) : 
  S with type 'a write_data := 'a M.t

Specialize a Write_port_1d.t given widths.

module Specialize_with_config
  (M : Hardcaml.Interface.S)
  (_ : Config.S) : 
  S with type 'a write_data := 'a M.t

Specialize a Write_port_1d.t given a memory configuration.

module M (X : Base.T1) : sig ... end

Shorthand useful for writing 'a Write_port_1d.M(Foo).t in type signatures.

val sexp_of_m__t : 
  (module For_deriving.Sexp_of_m) ->
  ( 'a -> Base.Sexp.t ) ->
  ( 'a, _ ) t ->
  Base.Sexp.t