Write_port_2d (hardcaml_xilinx.Hardcaml_xilinx.Memory_builder.Write_port

type ('a, 'write_data) t = {

vertical_index : 'a;

enable : 'a;

data : 'write_data Base.list;

}

val sexp_of_t : 
  ( 'a -> Sexplib0.Sexp.t ) ->
  ( 'write_data -> Sexplib0.Sexp.t ) ->
  ( 'a, 'write_data ) t ->
  Sexplib0.Sexp.t

val map : 
  ( 'a, 'data_a ) t ->
  f_write_data:( 'data_a -> 'data_b ) ->
  f:( 'a -> 'b ) ->
  ( 'b, 'data_b ) t

val and_enable : 
  with_:Hardcaml.Signal.t ->
  ( Hardcaml.Signal.t, 'a ) t ->
  ( Hardcaml.Signal.t, 'a ) t

module type S = sig ... end

module Specialize
  (M : Hardcaml.Interface.S)
  (_ : Widths_2d) : 
  S with type 'a write_data := 'a M.t

Specialize a Read_port_2d.t given widths.

module Specialize_with_config
  (M : Hardcaml.Interface.S)
  (_ : Config.S) : 
  S with type 'a write_data := 'a M.t

Specialize a Write_port_2d.t given a memory configuration.

module M (M : Base.T1) : sig ... end

Shorthand useful for writing 'a Write_port_2d.M(Foo).t in type signatures.

val sexp_of_m__t : 
  (module For_deriving.Sexp_of_m) ->
  ( 'a -> Base.Sexp.t ) ->
  ( 'a, 'data ) t ->
  Base.Sexp.t