Ram_port_with_clear (hardcaml_xilinx.Hardcaml_xilinx.Ram_port_with

type 'a t = {

port : 'a Ram_port.t;

clear_busy : 'a;

}

This wraps a Ram_port.t with a small state machine that on clear sets all memory location values to the clear_to value. While the memory is being cleared, the output clear_busy will be high. Writes and reads while in this state will be ignored.

The port signals require an extra mutliplexer delay for this function.

Note that use of other ports on the RAM for writing is discouraged during the clear operation. For maximum safety one can guard the write enable to the other port with

{other_port.write_enable &: ~:port_with_clear.clear_busy}

include Ppx_deriving_hardcaml_runtime.Interface.S with type 'a t := 'a t

val sexp_of_t : ( 'a -> Sexplib0.Sexp.t ) -> 'a t -> Sexplib0.Sexp.t

val iter : 'a t -> f:( 'a -> Base.unit ) -> Base.unit

val iter2 : 'a t -> 'b t -> f:( 'a -> 'b -> Base.unit ) -> Base.unit

val map : 'a t -> f:( 'a -> 'b ) -> 'b t

val map2 : 'a t -> 'b t -> f:( 'a -> 'b -> 'c ) -> 'c t

val to_list : 'a t -> 'a Base.list

val t : (Base.string * Base.int) t

include Base.Equal.S1 with type 'a t := 'a t

val equal : 'a Base__Equal.equal -> 'a t Base__Equal.equal

val port_names : Base.string t

RTL names specified in the interface definition - commonly also the OCaml field name.

val port_widths : Base.int t

Bit widths specified in the interface definition.

type tag

val tags : tag t

val to_alist : 'a t -> (tag * 'a) Base.list

Create association list indexed by tag.

val of_alist : (tag * 'a) Base.list -> 'a t

Create interface from association list indexed by tag.

val sum_of_port_widths : Base.int

Sum of all port widths specified in the interface definition.

module Unsafe_assoc_by_port_name : sig ... end

val zip : 'a t -> 'b t -> ('a * 'b) t

val zip3 : 'a t -> 'b t -> 'c t -> ('a * 'b * 'c) t

val zip4 : 'a t -> 'b t -> 'c t -> 'd t -> ('a * 'b * 'c * 'd) t

val zip5 : 'a t -> 'b t -> 'c t -> 'd t -> 'e t -> ('a * 'b * 'c * 'd * 'e) t

val map3 : 'a t -> 'b t -> 'c t -> f:( 'a -> 'b -> 'c -> 'd ) -> 'd t

val map4 : 
  'a t ->
  'b t ->
  'c t ->
  'd t ->
  f:( 'a -> 'b -> 'c -> 'd -> 'e ) ->
  'e t

val map5 : 
  'a t ->
  'b t ->
  'c t ->
  'd t ->
  'e t ->
  f:( 'a -> 'b -> 'c -> 'd -> 'e -> 'f ) ->
  'f t

val iter3 : 
  'a t ->
  'b t ->
  'c t ->
  f:( 'a -> 'b -> 'c -> Base.unit ) ->
  Base.unit

val iter4 : 
  'a t ->
  'b t ->
  'c t ->
  'd t ->
  f:( 'a -> 'b -> 'c -> 'd -> Base.unit ) ->
  Base.unit

val iter5 : 
  'a t ->
  'b t ->
  'c t ->
  'd t ->
  'e t ->
  f:( 'a -> 'b -> 'c -> 'd -> 'e -> Base.unit ) ->
  Base.unit

val fold : 'a t -> init:'acc -> f:( 'acc -> 'a -> 'acc ) -> 'acc

val fold2 : 'a t -> 'b t -> init:'acc -> f:( 'acc -> 'a -> 'b -> 'acc ) -> 'acc

val scan : 'a t -> init:'acc -> f:( 'acc -> 'a -> 'acc * 'b ) -> 'b t

val scan2 : 
  'a t ->
  'b t ->
  init:'acc ->
  f:( 'acc -> 'a -> 'b -> 'acc * 'c ) ->
  'c t

val offsets : ?rev:Base.bool -> Base.unit -> Base.int t

Offset of each field within the interface. The first field is placed at the least significant bit, unless the rev argument is true.

val of_interface_list : 'a t Base.list -> 'a Base.list t

Take a list of interfaces and produce a single interface where each field is a list.

val to_interface_list : 'a Base.list t -> 'a t Base.list

Create a list of interfaces from a single interface where each field is a list. Raises if all lists don't have the same length.

module All (M : Base.Monad.S) : sig ... end

Similar to Monad.all for lists -- combine and lift the monads to outside the interface.

val or_error_all : 'a Base.Or_error.t t -> 'a t Base.Or_error.t

Equivalent to All(Or_error).all. This is made a special case for convenience.

module type Comb = sig ... end

module Make_comb (Comb : Hardcaml.Comb.S) : Comb with type comb = Comb.t

module Of_bits : Comb with type comb = Hardcaml.Bits.t

module Of_signal : sig ... end

module Of_always : sig ... end

Helper functions to ease usage of the Always API when working with interfaces.

module Names_and_widths : sig ... end

val create : 
  clear_to:Hardcaml.Signal.t ->
  clear:Hardcaml.Signal.t ->
  clock:Hardcaml.Signal.t ->
  size:Base.int ->
  port:Hardcaml.Signal.t Ram_port.t ->
  Hardcaml.Signal.t t