Field_ops_lib.Adder_subtractor_pipeMultistage fully-pipelined ripple-carry-adder (or subtractor).
This module computs a OP b OP c OP d... in fully-piipelined using the ripple-carry-add algorithm. Each of the OP are either (+) or (-) (they don't have to be the same)
The fully-pipelined adder breaks the adder down to stages chunks, each to be added separately every clock cycles. Registers are placed at the inputs and outputs to align them to the same clock cycles.
If any but the first of the operands are constants, the module will generate a specialized module that uses the constant directly throughout the adder/subtractor, rather than pipelining it.
module Term_and_op : sig ... endmodule O : sig ... endOutput of the adder/subtractor with carry/borrow bits.
val mixed :
?name:string ->
?instance:string ->
stages:int ->
scope:Hardcaml.Scope.t ->
enable:Hardcaml.Signal.t ->
clock:Hardcaml.Signal.t ->
init:Hardcaml.Signal.t ->
Hardcaml.Signal.t Term_and_op.t list ->
Hardcaml.Signal.t O.tInstantiate a hierarchical pipelined adder/subtractor chain.
val add :
?name:string ->
?instance:string ->
stages:int ->
scope:Hardcaml.Scope.t ->
enable:Hardcaml.Signal.t ->
clock:Hardcaml.Signal.t ->
Hardcaml.Signal.t list ->
Hardcaml.Signal.t O.tSimilar to mixed, but only with additions.
val sub :
?name:string ->
?instance:string ->
stages:int ->
scope:Hardcaml.Scope.t ->
enable:Hardcaml.Signal.t ->
clock:Hardcaml.Signal.t ->
Hardcaml.Signal.t list ->
Hardcaml.Signal.t O.tSimilar to mixed, but only with subtractions.
val mixed_no_carry :
?name:string ->
?instance:string ->
stages:int ->
scope:Hardcaml.Scope.t ->
enable:Hardcaml.Signal.t ->
clock:Hardcaml.Signal.t ->
init:Hardcaml.Signal.t ->
Hardcaml.Signal.t Term_and_op.t list ->
Hardcaml.Signal.tThese are similar to the mixed, add and sub functions, but without the carry/borrow bits.
Note that stages = 0 or stages = 1 is allowed. It will result in a non-hierarchical combinational adder and a single-stage adder respectively. For adding values of stages, this module will instantiate a a hierarchical module. The rationale for this is we empirically observed better synthesis results when we don't instantiate it hierarchically.
val add_no_carry :
?name:string ->
?instance:string ->
stages:int ->
scope:Hardcaml.Scope.t ->
enable:Hardcaml.Signal.t ->
clock:Hardcaml.Signal.t ->
Hardcaml.Signal.t list ->
Hardcaml.Signal.tval sub_no_carry :
?name:string ->
?instance:string ->
stages:int ->
scope:Hardcaml.Scope.t ->
enable:Hardcaml.Signal.t ->
clock:Hardcaml.Signal.t ->
Hardcaml.Signal.t list ->
Hardcaml.Signal.t