Slave_to_master (zprize.Hardcaml_axi.Axi256.Lite.Slave_to

type !'a t = {

awready : 'a;

wready : 'a;

bresp : 'a;

bvalid : 'a;

arready : 'a;

rdata : 'a;

rresp : 'a;

rvalid : 'a;

}

val sexp_of_t : ( 'a -> Sexplib0.Sexp.t ) -> 'a t -> Sexplib0.Sexp.t

val iter : 'a t -> f:( 'a -> Base.unit ) -> Base.unit

val iter2 : 'a t -> 'b t -> f:( 'a -> 'b -> Base.unit ) -> Base.unit

val map : 'a t -> f:( 'a -> 'b ) -> 'b t

val map2 : 'a t -> 'b t -> f:( 'a -> 'b -> 'c ) -> 'c t

val to_list : 'a t -> 'a Base.list

val t : (Base.string * Base.int) t

val equal : 'a Base__Equal.equal -> 'a t Base__Equal.equal

val port_names : Base.string t

val port_widths : Base.int t

type tag

val tags : tag t

val to_alist : 'a t -> (tag * 'a) Base.list

val of_alist : (tag * 'a) Base.list -> 'a t

val sum_of_port_widths : Base.int

module Unsafe_assoc_by_port_name : sig ... end

val zip : 'a t -> 'b t -> ('a * 'b) t

val zip3 : 'a t -> 'b t -> 'c t -> ('a * 'b * 'c) t

val zip4 : 'a t -> 'b t -> 'c t -> 'd t -> ('a * 'b * 'c * 'd) t

val zip5 : 'a t -> 'b t -> 'c t -> 'd t -> 'e t -> ('a * 'b * 'c * 'd * 'e) t

val map3 : 'a t -> 'b t -> 'c t -> f:( 'a -> 'b -> 'c -> 'd ) -> 'd t

val map4 : 
  'a t ->
  'b t ->
  'c t ->
  'd t ->
  f:( 'a -> 'b -> 'c -> 'd -> 'e ) ->
  'e t

val map5 : 
  'a t ->
  'b t ->
  'c t ->
  'd t ->
  'e t ->
  f:( 'a -> 'b -> 'c -> 'd -> 'e -> 'f ) ->
  'f t

val iter3 : 
  'a t ->
  'b t ->
  'c t ->
  f:( 'a -> 'b -> 'c -> Base.unit ) ->
  Base.unit

val iter4 : 
  'a t ->
  'b t ->
  'c t ->
  'd t ->
  f:( 'a -> 'b -> 'c -> 'd -> Base.unit ) ->
  Base.unit

val iter5 : 
  'a t ->
  'b t ->
  'c t ->
  'd t ->
  'e t ->
  f:( 'a -> 'b -> 'c -> 'd -> 'e -> Base.unit ) ->
  Base.unit

val fold : 'a t -> init:'acc -> f:( 'acc -> 'a -> 'acc ) -> 'acc

val fold2 : 'a t -> 'b t -> init:'acc -> f:( 'acc -> 'a -> 'b -> 'acc ) -> 'acc

val scan : 'a t -> init:'acc -> f:( 'acc -> 'a -> 'acc * 'b ) -> 'b t

val scan2 : 
  'a t ->
  'b t ->
  init:'acc ->
  f:( 'acc -> 'a -> 'b -> 'acc * 'c ) ->
  'c t

val offsets : ?rev:Base.bool -> Base.unit -> Base.int t

val of_interface_list : 'a t Base.list -> 'a Base.list t

val to_interface_list : 'a Base.list t -> 'a t Base.list

module All (M : Base.Monad.S) : sig ... end

val or_error_all : 'a Base.Or_error.t t -> 'a t Base.Or_error.t

module type Comb = sig ... end

module Make_comb (Comb : Hardcaml.Comb.S) : sig ... end

module Of_bits : sig ... end

module Of_signal : sig ... end

module Of_always : sig ... end

module Names_and_widths : sig ... end