Hardcaml_ntt.BramDouble buffered (Ultra)ram blocks which provide 2 read and 2 write ports.
Internally we instantiate 2 seperate rams to provide the require port density. The write ports access one ram, while the read ports access the other. The flip signal swaps which rams are read and written.
val create :
Hardcaml.Scope.t ->
build_mode:Hardcaml.Build_mode.t ->
size:int ->
read_latency:int ->
clock:Hardcaml.Signal.t ->
port_a:Hardcaml.Signal.t Hardcaml_xilinx.Ram_port.t ->
port_b:Hardcaml.Signal.t Hardcaml_xilinx.Ram_port.t ->
Hardcaml.Signal.t * Hardcaml.Signal.ttype write_port = {address : Hardcaml.Signal.t; |
data : Hardcaml.Signal.t; |
enable : Hardcaml.Signal.t; |
}val create_dual :
Hardcaml.Scope.t ->
build_mode:Hardcaml.Build_mode.t ->
size:int ->
read_latency:int ->
clock:Hardcaml.Signal.t ->
clear:Hardcaml.Signal.t ->
flip:Hardcaml.Signal.t ->
write_port_a:write_port ->
write_port_b:write_port ->
read_port_a:read_port ->
read_port_b:read_port ->
Hardcaml.Signal.t * Hardcaml.Signal.t