Module Twisted_edwards_lib.Config

module Slr_assignments : sig ... end
type t = {
multiply : fn;
reduce : fn;
coarse_reduce : fn;
adder_stages : int;
subtractor_stages : int;
doubler_stages : int;
p : Z.t;
a : Z.t;
d : Z.t;
output_pipeline_stages : int;
arbitrated_multiplier : bool;
slr_assignments : Slr_assignments.t;
}
val coarse_reduce : t -> scope:Hardcaml.Scope.t -> clock:Hardcaml.Signal.t -> enable:Hardcaml.Signal.t -> Hardcaml.Signal.t -> Hardcaml.Signal.t
module Reduce : sig ... end
val multiply_latency : reduce:Reduce.t -> t -> int
module For_bls12_377 : sig ... end