Module Zprize_ntt

module For_vitis : sig ... end

Top-level wrapper with port naming to suit the Vivido Vitis infrastructure.

module Load_sm : sig ... end

Sequence the loading of coefficients from DRAM into the parallel MTT cores.

module Memory_layout : sig ... end
module Store_sm : sig ... end

Sequence the storing of coefficients from the parallel MTT cores into DRAM.

module Top : sig ... end

Instantiate the parallel NTT cores along with the load and store state machines.

module Top_config : sig ... end