Module Cyclesim.Config

type t = {
is_internal_port : ( Signal.t -> Base.bool ) Base.option;(*

Passed each signal in the design which has a name. Returns true if the simulator should expose it for reading in the testbench (or display in a waveform).

*)
combinational_ops_database : Combinational_ops_database.t;(*

Database of instantiations which may be replace by a combinational operation.

*)
compute_digest : Base.bool;(*

Compute an md5 digest of the outputs of a simulation run. Enabled by default within inlined tests.

*)
deduplicate_signals : Base.bool;(*

Perform a pass which finds structurally equal signals and shares them.

*)
store_circuit : Base.bool;(*

Stores the post-processed circuit that is used to compile the simulation. This should generally be set to false, so that the Circuit can be garbage collected once the simulation is constructed.

*)
}
val default : t
val trace : Base.bool -> t
val trace_all : t