Cyclesim (hardcaml.Hardcaml.Cyclesim)

module Port_list : sig ... end

module Digest : sig ... end

module Config : sig ... end

type ('i, 'o) t

base type of the cycle based simulators

type t_port_list = ( Port_list.t, Port_list.t ) t

val circuit : ( _, _ ) t -> Circuit.t Base.option

returns the circuit used to compile the simulation.

val cycle : ( _, _ ) t -> Base.unit

advance by 1 clock cycle (check->comb->seq->comb)

val cycle_check : ( _, _ ) t -> Base.unit

check inputs are valid before a simulation cycle

val cycle_before_clock_edge : ( _, _ ) t -> Base.unit

update combinatorial logic before clock edge and relative to new inputs.

val cycle_at_clock_edge : ( _, _ ) t -> Base.unit

update sequential logic - registers and memories.

val cycle_after_clock_edge : ( _, _ ) t -> Base.unit

update combinatorial logic after clock edge

val reset : ( _, _ ) t -> Base.unit

reset simulator

val in_port : ( _, _ ) t -> Base.string -> Bits.t Base.ref

get input port given a name

val internal_port : ( _, _ ) t -> Base.string -> Bits.t Base.ref

get a traced internal port given a name.

val out_port : 
  ?clock_edge:Side.t ->
  ( _, _ ) t ->
  Base.string ->
  Bits.t Base.ref

Get output port given a name. If clock_edge is Before the outputs are computed prior to the clock edge - After means the outputs are computed after the clock edge.

val inputs : ( 'i, _ ) t -> 'i

val outputs : ?clock_edge:Side.t -> ( _, 'o ) t -> 'o

val in_ports : ( _, _ ) t -> Port_list.t

val out_ports : ?clock_edge:Side.t -> ( _, _ ) t -> Port_list.t

val internal_ports : ( _, _ ) t -> Port_list.t

get list of internal nodes

val digest : ( _, _ ) t -> Digest.t Base.ref

val lookup_reg : ( _, _ ) t -> Base.string -> Bits.Mutable.t Base.option

Peek at internal registers, return Some _ if it's present. Note that the node must marked as traced in Cyclesim.Config.t when creating simulations for this to return (Some _). Writing to the Bits.Mutable.t will change the simulation internal node's value and affect the results of simulation.

val lookup_mem : 
  ( _, _ ) t ->
  Base.string ->
  Bits.Mutable.t Base.array Base.option

Similar to lookup_data, but for memories. This is very useful for initializing memory contents without having to simulate the entire circuit.

module Violated_or_not : sig ... end

val results_of_assertions : 
  ( _, _ ) t ->
  Violated_or_not.t Base.Map.M(Base.String).t

val create : ?config:Config.t -> Circuit.t -> t_port_list

construct a simulator from a circuit

module Combine_error : sig ... end

val combine : 
  ?port_sets_may_differ:Base.bool ->
  ?on_error:( Combine_error.t -> Base.unit ) ->
  ( 'i, 'o ) t ->
  ( 'i, 'o ) t ->
  ( 'i, 'o ) t

Combine 2 simulators. The inputs are set on the 1st simulator and copied to the 2nd. Outputs are checked and on_error is called if a difference is found. By default, on_error raises.

The simulators should have the same input and output port sets, unless port_sets_may_differ is true, in which case only ports which exist on both simulators are checked.

module With_interface (I : Interface.S) (O : Interface.S) : sig ... end

module Private : sig ... end