Module Cyclesim.Private

type port_list = Port_list.t
type task = Base.unit -> Base.unit
val create : ?circuit:Circuit.t -> in_ports:port_list -> out_ports_before_clock_edge:port_list -> out_ports_after_clock_edge:port_list -> internal_ports:port_list -> reset:task -> cycle_check:task -> cycle_before_clock_edge:task -> cycle_at_clock_edge:task -> cycle_after_clock_edge:task -> lookup_reg:( Base.string -> Bits.Mutable.t Base.option ) -> lookup_mem:( Base.string -> Bits.Mutable.t Base.array Base.option ) -> assertions:Bits.Mutable.t Base.Map.M(Base.String).t -> Base.unit -> t_port_list
module Step : sig ... end
val modify : ( 'i, 'o ) t -> (Side.t * Step.t * task) Base.list -> ( 'i, 'o ) t
val coerce : ( port_list, port_list ) t -> to_input:( port_list -> 'i ) -> to_output:( port_list -> 'o ) -> ( 'i, 'o ) t