Module Hardcaml.Parameter

A Parameter.t is the name and value of a configurable attribute of an instantiated RTL design.

In Verilog they are called parameterss and in VHDL they are called generics.

module Std_logic : sig ... end

9-state VHDL std_logic enumeration

module Std_logic_vector : Bits_list.Comb with type t = Std_logic.t Base.list
module Bit_vector : Bits_list.Comb with type t = Base.int Base.list
module Value : sig ... end
type t = {
name : Parameter_name.t;
value : Value.t;
}
val sexp_of_t : t -> Sexplib0.Sexp.t
include Base.Equal.S with type t := t
val equal : t Base__Equal.equal
val create : name:Base.string -> value:Value.t -> t
val find_name : t Base.list -> Parameter_name.t -> Value.t Base.Option.t
val find_name_exn : t Base.list -> Parameter_name.t -> Value.t
val is_subset : t Base.list -> t Base.list -> Base.bool

is_subset ts1 ts2 returns true iff every t in ts1 is in ts2.

val sort_by_name : t Base.list -> t Base.list