Module Hardcaml.Reg_spec

Definition of clock, reset and clear signals for sequential logic (ie registers).

include module type of struct include Signal.Reg_spec_ end

Reg_spec_ is a register specification. It is named Reg_spec_ rather than Reg_spec so that people consistently use the name Hardcaml.Reg_spec rather than Hardcaml.Signal.Reg_spec_.

type t
val sexp_of_t : t -> Sexplib0.Sexp.t
val create : ?clear:Hardcaml__Signal.t -> ?reset:Hardcaml__Signal.t -> Base.unit -> clock:Hardcaml__Signal.t -> t
val override : ?clock:Hardcaml__Signal.t -> ?clock_edge:Edge.t -> ?reset:Hardcaml__Signal.t -> ?reset_edge:Edge.t -> ?reset_to:Hardcaml__Signal.t -> ?clear:Hardcaml__Signal.t -> ?clear_level:Level.t -> ?clear_to:Hardcaml__Signal.t -> ?global_enable:Hardcaml__Signal.t -> t -> t
val clock : t -> Hardcaml__Signal.t
val clear : t -> Hardcaml__Signal.t
val reset : t -> Hardcaml__Signal.t