Module `Pipelined_adder.Short_latency`

Pipelined adder with a constant 2 cycle latency.

Florent de Dinechin, Hong Diep Nguyen, Bogdan Pasca. Pipelined FPGA Adders. International Conference on Field Programmable Logic and Applications, Aug 2010, Milano, Italy. pp.422-427, ff10.1109/FPL.2010.87ff. ffensl-00475780v2f

There is an output combinational delay of a single adder:

width / part_width.

The maximum delay is an adder of width:

max (width / part_width) (part_width*2)

val comb : 
  (module Hardcaml.Comb.S with type t = 'a) ->
  part_width:Base.int ->
  'a ->
  'a ->
  'a

Combinational version of the circuit. For testing.

val create : 
  part_width:Base.int ->
  clock:Hardcaml.Signal.t ->
  ?clear:Hardcaml.Signal.t ->
  Hardcaml.Signal.t ->
  Hardcaml.Signal.t ->
  Hardcaml.Signal.t

Sequential circuit with 2 cycle delay.