Module Hardcaml_circuits.Pipelined_adder

Pipelined adder architectures for very wide adders.

val create : part_width:Base.int -> clock:Hardcaml.Signal.t -> ?clear:Hardcaml.Signal.t -> ?c_in:Hardcaml.Signal.t -> Hardcaml.Signal.t -> Hardcaml.Signal.t -> Hardcaml.Signal.t

Pipelined adder. The result is available after (adder_width + partwidth) / part_width cycles.

module Short_latency : sig ... end

Pipelined adder with a constant 2 cycle latency.