Hardcaml_verilator.With_interface
module I : Hardcaml.Interface.S
module O : Hardcaml.Interface.S
val create :
( clock_names:string list ->
( Hardcaml.Signal.t I.t -> Hardcaml.Signal.t O.t ) ->
( Hardcaml.Bits.t Stdlib.ref I.t, Hardcaml.Bits.t Stdlib.ref O.t )
Hardcaml.Cyclesim.t )
with_options
Compiles a circuit and returns the shared object which can later be passed as the file_name
with Cache.Explicit to the cache
input.