Synthesis.Make_comb_primitives
module Synth : Xilinx_primitives
type t = Synth.t
val sexp_of_t : t -> Sexplib0.Sexp.t
include Base.Equal.S with type t := t
val equal : t Base__Equal.equal
val empty : t
the empty signal
val is_empty : t -> Base.bool
val width : t -> Base.int
returns the width of a signal
val of_constant : Hardcaml.Constant.t -> t
creates a constant
val to_constant : t -> Hardcaml.Constant.t
val to_string : t -> Base.string
create string from signal