Synthesis (hardcaml_xilinx.Hardcaml

module type Combinational_primitives = sig ... end

module type Sequential_primitives = sig ... end

module Lut_equation : sig ... end

Allow expressions to generate LUT init values

module Hardcaml_combinational_primitives
  (Comb : Hardcaml.Comb.S) : 
  Combinational_primitives with type t = Comb.t

Hardcaml based models of Xilinx primitives

module Hardcaml_sequential_primitives : Sequential_primitives

module Unisim_combinational_primitives : 
  Combinational_primitives with type t = Hardcaml.Signal.t

Unisim library based Xilinx primitives

module Unisim_sequential_primitives : Sequential_primitives

module type Xilinx_primitives = sig ... end

module type Lut_size = sig ... end

module Lut4 : Lut_size

module Lut6 : Lut_size

module Make_xilinx_primitives
  (X : Combinational_primitives)
  (L : Lut_size) : 
  Xilinx_primitives with type t = X.t

module Make_comb_primitives
  (Synth : Xilinx_primitives) : 
  Hardcaml.Comb.Primitives with type t = Synth.t

module Make_sequential
  (Synth : Xilinx_primitives with type t = Hardcaml.Signal.t) : 
  sig ... end