Modulo_adder_subtractor_pipe.With_interface
module M : sig ... end
module I : sig ... end
module O : sig ... end
val create :
stages:int ->
ops:[ `Add | `Sub ] list ->
rhs_constant_overrides:Hardcaml.Bits.t option list ->
Hardcaml.Scope.t ->
Hardcaml.Signal.t I.t ->
Hardcaml.Signal.t O.t