Module Field_ops_lib.Modulo_adder_subtractor_pipe

Multistage pipelined ripple-carry-adder (or subtractor), internally used to implement modulo_add and modulo_sub.

This module computes a `op1` b `op2` c `op3` d..., where each of the ops are either (+) or (-) (they don't have to be the same). The output of the module will contain all the results and carries of the following:

The generated architecture for a single pipeline stage for summing 3 numbers looks something like the following:

> LUT > CARRY8 > LUT > CARRY8
          ^              ^
> LUT > CARRY8 > LUT > CARRY8
          ^              ^
> LUT > CARRY8 > LUT > CARRY8
          ^              ^
> LUT > CARRY8 > LUT > CARRY8
module Single_op_output : sig ... end

Output from performing a single a `op1` b step.

module Term_and_op : sig ... end
module Input : sig ... end
val hierarchical : ?name:string -> ?instance:string -> stages:int -> scope:Hardcaml.Scope.t -> enable:Hardcaml.Signal.t -> clock:Hardcaml.Signal.t -> Hardcaml.Signal.t Input.t -> Hardcaml.Signal.t Single_op_output.t list

Instantiate a hierarchical pipelined adder/subtractor chain.

val create : (module Hardcaml.Comb.S with type t = 'a) -> stages:int -> pipe:( n:int -> 'a -> 'a ) -> 'a Input.t -> 'a Single_op_output.t list

Similar to hierarchical, but without hierarchy.

val add : ?name:string -> ?instance:string -> stages:int -> scope:Hardcaml.Scope.t -> enable:Hardcaml.Signal.t -> clock:Hardcaml.Signal.t -> Hardcaml.Signal.t list -> Hardcaml.Signal.t
val sub : ?name:string -> ?instance:string -> stages:int -> scope:Hardcaml.Scope.t -> enable:Hardcaml.Signal.t -> clock:Hardcaml.Signal.t -> Hardcaml.Signal.t -> Hardcaml.Signal.t list -> Hardcaml.Signal.t

sub ~stages ... a xs computes a - xs[0] - xs[1] ...

module With_interface (M : sig ... end) : sig ... end