Of_signal (zprize.Hardcaml_axi.Stream.Make.Source.Of

include Comb with type comb = Hardcaml.Signal.t

type comb = Hardcaml.Signal.t

type t = comb t

val sexp_of_t : t -> Sexplib0.Sexp.t

val sexp_of_t : comb t -> Sexplib0.Sexp.t

val assert_widths : comb t -> Base.unit

Raise if the widths of t do not match those specified in the interface.

val of_int : Base.int -> comb t

Each field is set to the constant integer value provided.

val const : Base.int -> comb t

val pack : ?rev:Base.bool -> comb t -> comb

Pack interface into a vector.

val unpack : ?rev:Base.bool -> comb -> comb t

Unpack interface from a vector.

val mux : comb -> comb t Base.list -> comb t

Multiplex a list of interfaces.

val mux2 : comb -> comb t -> comb t -> comb t

val concat : comb t Base.list -> comb t

Concatenate a list of interfaces.

val priority_select : 
  ( ( comb, comb t ) Hardcaml.Comb.with_valid2 Base.list ->
    ( comb, comb t ) Hardcaml.Comb.with_valid2 )
    Hardcaml.Comb.optional_branching_factor

val priority_select_with_default : 
  ( ( comb, comb t ) Hardcaml.Comb.with_valid2 Base.list ->
    default:comb t ->
    comb t )
    Hardcaml.Comb.optional_branching_factor

val onehot_select : 
  ( ( comb, comb t ) Hardcaml.Comb.with_valid2 Base.list ->
    comb t )
    Hardcaml.Comb.optional_branching_factor

val widths : t -> Base.int t

Actual bit widths of each field.

val of_ints : Base.int t -> t

consts c sets each field to the integer value in c using the declared field bit width.

val consts : Base.int t -> t

val wires : ?named:Base.bool -> ?from:t -> Base.unit -> t

Create a wire for each field. If named is true then wires are given the RTL field name. If from is provided the wire is attached to each given field in from.

val reg : ?enable:Hardcaml.Signal.t -> Hardcaml.Reg_spec.t -> t -> t

Defines a register over values in this interface. enable defaults to vdd.

val pipeline : 
  ?attributes:Hardcaml.Rtl_attribute.t Base.list ->
  ?enable:Hardcaml.Signal.t ->
  n:Base.int ->
  Hardcaml.Reg_spec.t ->
  t ->
  t

Defines a register pipeline over values in this interface. enable defaults to vdd and attributes defaults to an empty list.

val assign : t -> t -> Base.unit

val (<==) : t -> t -> Base.unit

val inputs : Base.unit -> t

inputs t is wires () ~named:true.

val outputs : t -> t

outputs t is wires () ~from:t ~named:true.

val apply_names : 
  ?prefix:Base.string ->
  ?suffix:Base.string ->
  ?naming_op:( Hardcaml.Signal.t -> Base.string -> Hardcaml.Signal.t ) ->
  t ->
  t

Apply name to field of the interface. Add prefix and suffix if specified.

val validate : t -> Base.unit

Checks the port widths of the signals in the interface. Raises if they mismatch.