With_rams (zprize.Hardcaml_ntt.Single_core.With

Parameters

module Config : Core_config.S

Signature

module Core : sig ... end

module I : sig ... end

module O : sig ... end

val input_ram : 
  Hardcaml.Scope.t ->
  Hardcaml.Build_mode.t ->
  clock:Hardcaml.Signal.t ->
  clear:Hardcaml.Signal.t ->
  flip:Hardcaml.Signal.t ->
  wr_addr:Hardcaml.Signal.t ->
  wr_d:Hardcaml.Signal.t ->
  wr_en:Hardcaml.Signal.t ->
  addr1_in:Hardcaml.Signal.t ->
  addr2_in:Hardcaml.Signal.t ->
  read_enable_in:Hardcaml.Signal.t ->
  Hardcaml.Signal.t * Hardcaml.Signal.t

val transpose_ram : 
  Hardcaml.Scope.t ->
  Hardcaml.Build_mode.t ->
  clock:Hardcaml.Signal.t ->
  clear:Hardcaml.Signal.t ->
  addr1_in:Hardcaml.Signal.t ->
  addr1_out:Hardcaml.Signal.t ->
  q1:Hardcaml.Signal.t ->
  addr2_in:Hardcaml.Signal.t ->
  addr2_out:Hardcaml.Signal.t ->
  q2:Hardcaml.Signal.t ->
  read_enable_in:Hardcaml.Signal.t ->
  write_enable_out:Hardcaml.Signal.t ->
  flip:Hardcaml.Signal.t ->
  last_stage:Hardcaml.Signal.t ->
  Hardcaml.Signal.t * Hardcaml.Signal.t

val output_ram : 
  Hardcaml.Scope.t ->
  Hardcaml.Build_mode.t ->
  clock:Hardcaml.Signal.t ->
  clear:Hardcaml.Signal.t ->
  flip:Hardcaml.Signal.t ->
  last_stage:Hardcaml.Signal.t ->
  twiddle_stage:Hardcaml.Signal.t ->
  rd_addr:Hardcaml.Signal.t ->
  rd_en:Hardcaml.Signal.t ->
  addr1_out:Hardcaml.Signal.t ->
  q1:Hardcaml.Signal.t ->
  addr2_out:Hardcaml.Signal.t ->
  q2:Hardcaml.Signal.t ->
  write_enable_out:Hardcaml.Signal.t ->
  Hardcaml.Signal.t

val create : 
  ?row:Base.int ->
  build_mode:Hardcaml.Build_mode.t ->
  Hardcaml.Scope.t ->
  Hardcaml.Signal.t Hardcaml.Interface.Create_fn(I)(O).t

val hierarchy : 
  ?row:Base.int ->
  ?instance:Base.string ->
  build_mode:Hardcaml.Build_mode.t ->
  Hardcaml.Scope.t ->
  Hardcaml.Signal.t Hardcaml.Interface.Create_fn(I)(O).t