Module Msm_pippenger

module Compact_stream : sig ... end

Takes An AXI512 stream from DDR and converts it into a 256 bit stream, useful for crossing SLRs when not bandwidth bound.

module Config : sig ... end
module Config_intf : sig ... end
module Config_utils : sig ... end
module Full_controller : sig ... end

Wraps multiple individual pippenger controllers with helper logic and FIFOs to create one that can utilize a fully pipelined adder.

module Host_to_msm : sig ... end

Converts a 512 bit axi stream of scalars + points (scalar and point coordinates are 64 bit aligned). This then drives the MSM pippenger top level.

module Host_to_msm_simple : sig ... end
module Kernel_for_vitis : sig ... end

Wraps the MSM pippenger top module with 512 bit AXI stream interfaces that can be driven by the AWS shell when compiled with Vitis.

module Merge_axi_streams : sig ... end

Merges multiple AXI streams into one. This is used so that points can be pre-loaded into DDR and only scalars need to be streamed over PCIe at runtime.

module Msm_result_to_host : sig ... end

Takes in points from the MSM block and packs them input a 512bit stream where every coordinate and point has been aligned to 64 bits, and can then be sent up to a central controller and back to the host.

module Scalar_transformation : sig ... end

Module to transform scalars to a signed-digit representation, which is expected by the downstream FPGA logic.

module Top : sig ... end

Computes the MSM over a stream of input points and scalars.

module Window_ram : sig ... end
module Window_ram_partition : sig ... end