Msm_pippenger.Window_ram
module Partition : sig ... end
val named_register : ?clear:Hardcaml.Signal.t -> scope:Hardcaml.Scope.t -> clock:Hardcaml__Signal.t -> slr:int option -> Hardcaml.Signal.t -> Hardcaml.Signal.t
module Make (M : sig ... end) : sig ... end