Of_always (hardcaml.Hardcaml.Interface.Update.Of

val value : Always.Variable.t t -> Signal.t t

val assign : Always.Variable.t t -> Signal.t t -> Always.t

Assign a interface containing variables in an always block.

val reg : ?enable:Signal.t -> Reg_spec.t -> Always.Variable.t t

Creates a interface container with register variables.

val wire : ( Base.int -> Signal.t ) -> Always.Variable.t t

Creates a interface container with wire variables, e.g. Foo.Of_always.wire Signal.zero, which would yield wires defaulting to zero.