I (zprize.Msm_pippenger.Window_ram

module Ram_port : sig ... end

type 'a t = {

clock : 'a;

port_a : 'a Ram_port.t;

port_b : 'a Ram_port.t;

}

val sexp_of_t : ( 'a -> Sexplib0.Sexp.t ) -> 'a0 t -> Sexplib0.Sexp.t

val iter : 'a t -> f:( 'a0 -> Base.unit ) -> Base.unit

val iter2 : 'a t -> 'b t -> f:( 'a0 -> 'b0 -> Base.unit ) -> Base.unit

val map : 'a t -> f:( 'a0 -> 'b ) -> 'b0 t

val map2 : 'a t -> 'b t -> f:( 'a0 -> 'b0 -> 'c ) -> 'c0 t

val to_list : 'a t -> 'a0 Base.list

val t : (Base.string * Base.int) t

val equal : 'a Base__Equal.equal -> 'a0 t Base__Equal.equal

val port_names : Base.string t

val port_widths : Base.int t

type tag

val tags : tag t

val to_alist : 'a t -> (tag * 'a0) Base.list

val of_alist : (tag * 'a) Base.list -> 'a0 t

val sum_of_port_widths : Base.int

module Unsafe_assoc_by_port_name : sig ... end

val zip : 'a t -> 'b t -> ('a0 * 'b0) t

val zip3 : 'a t -> 'b t -> 'c t -> ('a0 * 'b0 * 'c0) t

val zip4 : 'a t -> 'b t -> 'c t -> 'd t -> ('a0 * 'b0 * 'c0 * 'd0) t

val zip5 : 
  'a t ->
  'b t ->
  'c t ->
  'd t ->
  'e t ->
  ('a0 * 'b0 * 'c0 * 'd0 * 'e0) t

val map3 : 'a t -> 'b t -> 'c t -> f:( 'a0 -> 'b0 -> 'c0 -> 'd ) -> 'd0 t

val map4 : 
  'a t ->
  'b t ->
  'c t ->
  'd t ->
  f:( 'a0 -> 'b0 -> 'c0 -> 'd0 -> 'e ) ->
  'e0 t

val map5 : 
  'a t ->
  'b t ->
  'c t ->
  'd t ->
  'e t ->
  f:( 'a0 -> 'b0 -> 'c0 -> 'd0 -> 'e0 -> 'f ) ->
  'f0 t

val iter3 : 
  'a t ->
  'b t ->
  'c t ->
  f:( 'a0 -> 'b0 -> 'c0 -> Base.unit ) ->
  Base.unit

val iter4 : 
  'a t ->
  'b t ->
  'c t ->
  'd t ->
  f:( 'a0 -> 'b0 -> 'c0 -> 'd0 -> Base.unit ) ->
  Base.unit

val iter5 : 
  'a t ->
  'b t ->
  'c t ->
  'd t ->
  'e t ->
  f:( 'a0 -> 'b0 -> 'c0 -> 'd0 -> 'e0 -> Base.unit ) ->
  Base.unit

val fold : 'a t -> init:'acc -> f:( 'acc -> 'a0 -> 'acc ) -> 'acc

val fold2 : 
  'a t ->
  'b t ->
  init:'acc ->
  f:( 'acc -> 'a0 -> 'b0 -> 'acc ) ->
  'acc

val scan : 'a t -> init:'acc -> f:( 'acc -> 'a0 -> 'acc * 'b ) -> 'b0 t

val scan2 : 
  'a t ->
  'b t ->
  init:'acc ->
  f:( 'acc -> 'a0 -> 'b0 -> 'acc * 'c ) ->
  'c0 t

val offsets : ?rev:Base.bool -> Base.unit -> Base.int t

val of_interface_list : 'a t Base.list -> 'a0 Base.list t

val to_interface_list : 'a Base.list t -> 'a0 t Base.list

module All (M : Base.Monad.S) : sig ... end

val or_error_all : 'a Base.Or_error.t t -> 'a0 t Base.Or_error.t

module type Comb = sig ... end

module Make_comb (Comb : Hardcaml.Comb.S) : sig ... end

module Of_bits : sig ... end

module Of_signal : sig ... end

module Of_always : sig ... end

module Names_and_widths : sig ... end