Window_ram_partition.Makemodule M : sig ... endmodule I : sig ... endmodule O : sig ... endval create : 
  build_mode:Hardcaml.Build_mode.t ->
  b_write_data:Hardcaml.Signal.t ->
  Hardcaml.Scope.t ->
  Hardcaml__Signal.t I.t ->
  Hardcaml.Signal.t O.tb_write_data is a constant, so it doesn't need any registers around * it.
val hierarchical : 
  ?instance:Base.string ->
  b_write_data:Hardcaml.Signal.t ->
  build_mode:Hardcaml.Build_mode.t ->
  Hardcaml.Scope.t ->
  Hardcaml.Signal.t I.t ->
  Hardcaml.Signal.t O.t