Mixed_add_precompute.Make
module Num_bits : Num_bits.S
module Xyt : sig ... end
module Xyzt : sig ... end
module I : sig ... end
module O : sig ... end
val latency : Config.t -> int
val create :
?build_mode:Hardcaml.Build_mode.t ->
config:Config.t ->
Hardcaml.Scope.t ->
Hardcaml.Signal.t I.t ->
Hardcaml.Signal.t O.t
val hierarchical :
?build_mode:Hardcaml.Build_mode.t ->
?instance:string ->
config:Config.t ->
Hardcaml.Scope.t ->
Hardcaml.Signal.t Hardcaml.Interface.Create_fn(I)(O).t