Of_always (zprize.Hardcaml_axi.Axi256.Lite.Register_bank.1-Rd.Of

val value : Hardcaml.Always.Variable.t t -> Hardcaml.Signal.t t

val assign : 
  Hardcaml.Always.Variable.t t ->
  Hardcaml.Signal.t t ->
  Hardcaml.Always.t

Assign a interface containing variables in an always block.

val reg : 
  ?enable:Hardcaml.Signal.t ->
  Hardcaml.Reg_spec.t ->
  Hardcaml.Always.Variable.t t

Creates a interface container with register variables.

val wire : ( Base.int -> Hardcaml.Signal.t ) -> Hardcaml.Always.Variable.t t

Creates a interface container with wire variables, e.g. Foo.Of_always.wire Signal.zero, which would yield wires defaulting to zero.