Host Driver Software
Our host driver performs the following preprocessing ahead of any evaluations
- Transform the affine points from Weierstrass form into our internal affine point format based on scaled Twisted Edwards curves (See the page on mixed point addition for the formulae of the transformation.)
- Transfer the preprocessed points into the FPGA
It performs the following when evaluating MSMs in
- Transfers scalars to the DDR
- Startup Xilinx Vitis kernels to transfer (scalar & points) from DDR to the MSM evaluation blocks for performing bucket aggregation
- Startup Xilinx Vitis kernels to transfer pippenger bucket results back to the host
- Perform final bucket sum
The host driver interleaves most of the CPU work with the FPGA work to reduce total latency when evaluating a batch of multiple MSMs:
- Start the MSM evaluation before transfering all the scalars into the host.
- Transfer scalars for the next MSM evaluation while the first evaluation has not completed.
- Evaluate the next MSM’s bucket aggregation on the FPGA while computing the current MSM’s bucket sum on the host.
Our host driver expects the prime field elements to be in Montgomery form, as our competition test harness interfaces with the Arkworks library which internally represents field elements in this form. This representation incurs a ~10us penalty per MSM evaluation, which is insignificant for large MSMs.
Our host driver uses the Xilinx XRT library with openCL for host to/from FPGA communication, and gmp for any on-host computation. Code for our host driver is available here.